Applying semiconductor technology, network-on-chips (NOCs) are designed on silicon chips to expand on-chip communications. Three-dimensional (3D) mesh-based architecture is also known as a basic NOC architecture characterized by better energy consumption and latency compared with two-dimensional (2D) ones. Recently developed architectures are based on the regular mesh. However, there are serious drawbacks in NOC architectures including high power consumption, energy consumption, and latency. Therefore, improving topology diameter would overcome these shortcomings. Accordingly, a new 3D mesh-based NOC architecture is proposed in the present study utilizing the star node, consisting of a new 3D topology with a small diameter and new deadlock-free routing. The diameter of this architecture is then compared with its counterparts. Afterward, the scalable universal matrix multiplication algorithm (SUMMA) is implemented in the proposed architecture. The results indicate a smaller network diameter, lower energy consumption (32%), less network latency (8. 6%), as well as enhancement in throughput average (13. 6%). The proposed matrix multiplication algorithm also implies improvement in the cost of the proposed architecture in comparison with its counterparts.

The Micro Packet Switched based Network on Chip (NOC) is emerged to address traditional non-scalable buses-based Systems on Chip (SoC) challenges such as out of order transactions, flow control and higher latencies. The NOC is disposable to a different of defects in its life which cause of such drawbacks as data missing, efficiency reduction, and eventually, entire system overwhelm. This paper is amid to propose a new Offline-Structural Distributed Test Mechanism (OSDTM) to discovering and emplacing shorts on the data links in NOC. The projected test approach encompasses three main component namely Test Pattern Producer (TPP), Test Response Compiler (TRC) that are implanted in the Network Adapter (N) as well as a Flit Comparator Block (FCB) located in the Routers(R). The FCB concern is to detect dissimilar Flits through comparison the entrance Flits. The OSDTM leads to 100% Test Coverage (TC), 82. 3% Discovering Capability (DC), and 100% fault emplacement (FE) of faulty links in NOC. The experimental results illustrate that the FCB hardware cost is very insignificant in related to the hardware of Vici router.

This paper proposes a novel routing algorithm and test strategy which provides deadlock-freedom, low packet dropping and low latency in networks-on-chip (NOCs).We first propose an algorithm, in which functionality of a router is revised in order to enable it to test its own, as well as the preceding router’s, functionality. The recognized faults are reported to successive routers along the packet’s path to the destination without the need for generating any extra non-data packet. Furthermore, we enrich the initial scheme by adding several features such as ability to backtrack the misled packets, prediction of the safest path to destination, and clearance of transient faults. We show that the enriched approach, namely RSFR, demonstrates a significant performance improvement in terms of latency, drop-rate and fault coverage while retaining deadlock-freedom. The experimental results illustrate that fault coverage for routers can reach up to almost 100% with yet low power consumption.

Complex homogeneous network-on-chip or heterogeneous network-on-chip increases the need of determining and developing simulation tools for designer to evaluate and comparison network performance. Towards this end, ARTEMIS tool, a matlab based simulator environment is developed. This simulator offers some collections of network configuration regarding to the topology graph, routing algorithm and switching strategy, including allocation scheme for a target application. Consequently, designers can choose the number and depth of virtual channels and the capacity of each link by applying an efficient allocation scheme, which is provided by this tool. Average latency and throughput are evaluation performance metrics that are measured with proposed simulator tool.